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W9812G6JH
5. PIN DESCRIPTION
PIN NUMBER
23 ? 26, 22,
29 ? 35
20, 21
2, 4, 5, 7, 8,
10, 11, 13, 42,
44, 45, 47, 48,
PIN NAME
A0 ? A11
BS0, BS1
DQ0 ?
DQ15
FUNCTION
Address
Bank Select
Data Input/
Output
DESCRIPTION
Multiplexed pins for row and column address.
Row address: A0 ? A11. Column address: A0 ? A8.
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
Multiplexed pins for data output and input.
50, 51, 53
Disable or enable the command decoder. When
19
CS
Chip Select
command decoder is disabled, new command is
ignored and previous operation continues.
18
17
16
RAS
CAS
WE
Row Address
Strobe
Column Address
Strobe
Write Enable
Command input. When sampled at the rising edge of
the clock, RAS , CAS and WE define the
operation to be executed.
Referred to RAS
Referred to RAS
The output buffer is placed at Hi-Z (with latency of 2)
39, 15
LDQM,
UDQM
Input/Output
Mask
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
38
CLK
Clock Inputs
System clock used to sample inputs on the rising edge
of clock.
CKE controls the clock activation and deactivation.
37
CKE
Clock Enable
When CKE is low, Power Down mode, Suspend mode
or Self Refresh mode is entered.
1, 14, 27
28, 41, 54
3, 9, 43, 49
6, 12, 46, 52
36, 40
V DD
V SS
V DDQ
V SSQ
NC
Power (+3.3V)
Ground
Power (+3.3V)
for I/O Buffer
Ground for I/O
Buffer
No Connection
Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside DRAM.
Separated power from V DD , used for output buffers to
improve noise.
Separated ground from V SS , used for output buffers to
improve noise.
No connection
Publication Release Date: Jun. 25, 2013
-5-
Revision A06
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